URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_0/] - Rev 102

Rev	Log message	Author	Age	Path
102	update for changes in address space of external memory	arniml	7392d 06h	/t48/tags/rel_1_0/
101	assert p2_read_p2_o when expander port is read	arniml	7392d 06h	/t48/tags/rel_1_0/
100	reorder data_o generation	arniml	7392d 06h	/t48/tags/rel_1_0/
99	initial check-in	arniml	7392d 06h	/t48/tags/rel_1_0/
98	Fix bug "ANL and ORL to P1/P2 read port status instead of port output register"	arniml	7392d 06h	/t48/tags/rel_1_0/
97	initial check-in	arniml	7392d 07h	/t48/tags/rel_1_0/
96	select dedicated directorie(s) for regression	arniml	7393d 04h	/t48/tags/rel_1_0/
95	check counter inactivity	arniml	7393d 04h	/t48/tags/rel_1_0/
94	initial check-in	arniml	7393d 04h	/t48/tags/rel_1_0/
93	add support for line coverage evaluation with gcov	arniml	7393d 05h	/t48/tags/rel_1_0/
92	work around bug in Quartus II 4.0	arniml	7393d 05h	/t48/tags/rel_1_0/
91	fix edge detector bug for counter	arniml	7393d 05h	/t48/tags/rel_1_0/
90	intial check-in	arniml	7393d 05h	/t48/tags/rel_1_0/
89	initial check-in	arniml	7407d 01h	/t48/tags/rel_1_0/
88	allow memory bank switching during interrupts	arniml	7408d 03h	/t48/tags/rel_1_0/
87	abort gracfullt if memory bank switching does not work	arniml	7408d 03h	/t48/tags/rel_1_0/
86	update notice about expander port instructions	arniml	7408d 08h	/t48/tags/rel_1_0/
85	initial check-in	arniml	7408d 08h	/t48/tags/rel_1_0/
84	add if_timing module	arniml	7414d 00h	/t48/tags/rel_1_0/
83	connect if_timing to P2 output of T48	arniml	7414d 00h	/t48/tags/rel_1_0/