URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

[/] [tv80/] [trunk/] [rtl/] - Rev 116

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Rev	Log message	Author	Age	Path
111	Fixed inverted wait_n in tv80 core, updated sc_env environment	ghutchis	4791d 01h	/tv80/trunk/rtl/
109	Removed mreq_n from cfgo_driver, disconnected interrupt line	ghutchis	4875d 08h	/tv80/trunk/rtl/
107	Fixed memory contention between config interface and TV80 during write	ghutchis	4875d 17h	/tv80/trunk/rtl/
105	Fixed bugs after environment bringup	ghutchis	4875d 18h	/tv80/trunk/rtl/
103	Updated RTL syntax errors	ghutchis	4876d 01h	/tv80/trunk/rtl/
101	Added sample application for local config processor	ghutchis	4876d 07h	/tv80/trunk/rtl/
100	Changed do to dout in tv80n, checked in fix for flags bug	ghutchis	4907d 05h	/tv80/trunk/rtl/
90	Fixed syntax errors in core preventing Verilator from compiling. Added new capability to register generator to make registers which latch on an external event. Removed spurious copyright notice.	ghutchis	5323d 02h	/tv80/trunk/rtl/
89	RTL and environment fixes for nmi bug	ghutchis	5343d 05h	/tv80/trunk/rtl/
88	Fixed bug introduced by conversion of mcycle to one-hot FSM	ghutchis	5344d 20h	/tv80/trunk/rtl/
87	Added additional ifdef signals to remove unneede R (refresh) register	ghutchis	5360d 04h	/tv80/trunk/rtl/
84	New directory structure.	root	5583d 15h	/tv80/trunk/rtl/
83	Some fixes from Guy-- replace case with casex.	hharte	5656d 22h	/trunk/rtl/
82	Clean up spacing	hharte	5666d 18h	/trunk/rtl/
81	Initial version of TV80 Wishbone Wrapper	hharte	5666d 18h	/trunk/rtl/
80	Misc. code clean-up on mcode to make code smaller and (hopefully) more readable.	ghutchis	6766d 06h	/trunk/rtl/
78	Hajime Ishitani pointed out missing invert on cs_n signal	ghutchis	6809d 08h	/trunk/rtl/
74	Changed default for T2Write to be 1, to match expected behavior for most users.	ghutchis	6920d 09h	/trunk/rtl/
71	Ported UART from T80	ghutchis	6993d 08h	/trunk/rtl/
65	Major restructuring of simple_gmii block. 1) Changed simple_gmii block to simple_gmii_core 2) Migrated RAM instances out of core into top level 3) Removed CPU interface logic and created CPU interface block using register generator 4) Changed status register to interrupt register and added interrupt logic	ghutchis	7052d 03h	/trunk/rtl/

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Subversion Repositories tv80

[/] [tv80/] [trunk/] [rtl/] - Rev 116

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