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[/] [versatile_fifo/] [trunk/] [rtl/] [verilog/] - Rev 32

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Rev Log message Author Age Path
32 fixed SYN directives marcus.erlandsson 4997d 21h /versatile_fifo/trunk/rtl/verilog/
31 port map unneback 5068d 14h /versatile_fifo/trunk/rtl/verilog/
30 port map unneback 5068d 15h /versatile_fifo/trunk/rtl/verilog/
29 ACTEL syn define unneback 5076d 12h /versatile_fifo/trunk/rtl/verilog/
28 ACTEL async dual way FIFO unneback 5083d 21h /versatile_fifo/trunk/rtl/verilog/
27 initial commit, dual way simplex FIFO unneback 5084d 13h /versatile_fifo/trunk/rtl/verilog/
26 added ACTEL synthesis directive as define, +ACTEL unneback 5084d 13h /versatile_fifo/trunk/rtl/verilog/
25 DFF SR as separate logic unneback 5224d 09h /versatile_fifo/trunk/rtl/verilog/
24 updated fifo interfaces with re/rd and we/wr unneback 5224d 23h /versatile_fifo/trunk/rtl/verilog/
23 unneback 5227d 11h /versatile_fifo/trunk/rtl/verilog/
22 async fifo with multiple queues unneback 5227d 12h /versatile_fifo/trunk/rtl/verilog/
21 added DFF SR unneback 5241d 10h /versatile_fifo/trunk/rtl/verilog/
18 ADDR and DATA width set to 8 resp 32 unneback 5243d 13h /versatile_fifo/trunk/rtl/verilog/
17 based on updated versatile counter unneback 5247d 11h /versatile_fifo/trunk/rtl/verilog/
16 changed power of two style unneback 5510d 21h /versatile_fifo/trunk/rtl/verilog/
15 doc updated
gray_counter_defines added
dual port RAM updated		 unneback 5514d 15h /versatile_fifo/trunk/rtl/verilog/
13 adr update unneback 5559d 23h /versatile_fifo/trunk/rtl/verilog/
12 no mux on dual port mem read unneback 5572d 17h /versatile_fifo/trunk/rtl/verilog/
11 name conflict
wptr1 changed to wptr1_cnt etc		 unneback 5572d 19h /versatile_fifo/trunk/rtl/verilog/
10 rptr2 unneback 5572d 21h /versatile_fifo/trunk/rtl/verilog/

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