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[/] [xgate/] [trunk/] [bench/] - Rev 97

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Rev Log message Author Age Path
95 Covers all 127 interrupts with one service routine. rehayes 4596d 16h /xgate/trunk/bench/
94 Update irq test to check all interrupts, add sync reset test. All this to improve code coverage. rehayes 4596d 16h /xgate/trunk/bench/
93 Initial revision, memory image for skipjack test. rehayes 4596d 16h /xgate/trunk/bench/
89 Code cleanup. rehayes 4610d 15h /xgate/trunk/bench/
86 Add JTAG test tasks rehayes 4810d 15h /xgate/trunk/bench/
82 Added debug module to assist in software debugging. rehayes 5085d 18h /xgate/trunk/bench/
73 Code cleanup, eliminated index 0 of input and output interrupts. rehayes 5175d 22h /xgate/trunk/bench/
68 Added new test for interrupt priority and updated WISHBONE slave module with semaphore register. rehayes 5177d 01h /xgate/trunk/bench/
65 Parameterize delays based on number of RAM wait states. rehayes 5196d 21h /xgate/trunk/bench/
62 Cleanup implicit wire declarations. rehayes 5206d 21h /xgate/trunk/bench/
60 Add ability at insert wait states on RAM access rehayes 5213d 21h /xgate/trunk/bench/
54 complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module. rehayes 5282d 00h /xgate/trunk/bench/
50 incremental update to match status bit changes rehayes 5297d 21h /xgate/trunk/bench/
41 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5332d 21h /xgate/trunk/bench/
39 delete rehayes 5361d 00h /xgate/trunk/bench/
37 RAM model breakout for testbench rehayes 5361d 01h /xgate/trunk/bench/
36 Added bus arbitration for slave bus, but not fully functional yet. Added byte lane selects to task calls. rehayes 5361d 01h /xgate/trunk/bench/
35 Add byte lane select input to all tasks rehayes 5361d 01h /xgate/trunk/bench/
27 Subversion test, no actual code changes rehayes 5385d 19h /xgate/trunk/bench/
21 Added timeout, total error count, and XGCHN test rehayes 5393d 20h /xgate/trunk/bench/

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