URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] [trunk/] [rtl/] [verilog/] - Rev 92

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
92	Add sync reset to bypass register.	rehayes	4646d 14h	/xgate/trunk/rtl/verilog/
89	Code cleanup.	rehayes	4660d 13h	/xgate/trunk/rtl/verilog/
88	Updated with complete code	rehayes	4733d 22h	/xgate/trunk/rtl/verilog/
87	First pass JTAG TAP, state machine working but needs work to complete reset of TAP.	rehayes	4860d 12h	/xgate/trunk/rtl/verilog/
75	Fixed xlink synthesis warnings noted by Nachiket Jugade, missing else statment for chid_sm_ns line 393, mising default on shifter lines 2382	rehayes	5220d 19h	/xgate/trunk/rtl/verilog/
72	Code cleanup, eliminated index 0 of input and output interrupts.	rehayes	5225d 20h	/xgate/trunk/rtl/verilog/
67	Added irq bypass function and controll registers. Made lowest interrupt index highest priority.	rehayes	5226d 23h	/xgate/trunk/rtl/verilog/
64	Fixed more bugs related to wait states and debug mode.	rehayes	5246d 19h	/xgate/trunk/rtl/verilog/
63	Remove historical output ports that are no longer used.	rehayes	5256d 18h	/xgate/trunk/rtl/verilog/
59	Fix bug in entering DEBUG mode from WB bus command	rehayes	5263d 18h	/xgate/trunk/rtl/verilog/
57	Traded 16 data registers for 5 address regester when wait states are enabled.	rehayes	5315d 21h	/xgate/trunk/rtl/verilog/
53	Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal.	rehayes	5331d 22h	/xgate/trunk/rtl/verilog/
47	Fix status bit error in ADC and SBC instruction, fix error in thread startup.	rehayes	5347d 19h	/xgate/trunk/rtl/verilog/
43	Update for single program counter added, WISHBONE Slave bus word addressability and byte selection	rehayes	5381d 16h	/xgate/trunk/rtl/verilog/
42	Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection	rehayes	5381d 16h	/xgate/trunk/rtl/verilog/
41	Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection	rehayes	5382d 18h	/xgate/trunk/rtl/verilog/
40	Update for single program counter adder	rehayes	5402d 21h	/xgate/trunk/rtl/verilog/
34	minor changes related to wishbone master interface	rehayes	5410d 23h	/xgate/trunk/rtl/verilog/
31	Cleanup for MAX_CHANNEL bus	rehayes	5422d 18h	/xgate/trunk/rtl/verilog/
30	Added pins debud_mode_i and secure_mode_i. Cleanup for xgif bus	rehayes	5422d 18h	/xgate/trunk/rtl/verilog/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories xgate

[/] [xgate/] [trunk/] [rtl/] [verilog/] - Rev 92

Filtering Options