Rev |
Log message |
Author |
Age |
Path |
168 |
An updated version of the intensive CPU test. This one runs from C, and
requires a UART port and a PIC, but can run quite successfully on multiple
SoCs that have been built with the ZipCPU internal to them. |
dgisselq |
2911d 03h |
/zipcpu/trunk/bench/ |
159 |
Now supports building a simulator that can load ELF files, such as GCC and/or
binutils will produce. |
dgisselq |
2942d 23h |
/zipcpu/trunk/bench/ |
155 |
Improved debug trace quality, for finding bugs after the fact. |
dgisselq |
2943d 00h |
/zipcpu/trunk/bench/ |
154 |
Added timing checks on the busy and valid signals: either one of the two is
valid, or the whole is idle. |
dgisselq |
2943d 00h |
/zipcpu/trunk/bench/ |
152 |
Updated to match the new/updated multiply instructions. Of course, this is
still hand optimized and not compiled--so it's not really a true and proper
test (yet), but ... it's what I have. |
dgisselq |
2975d 22h |
/zipcpu/trunk/bench/ |
151 |
Minor formatting change. |
dgisselq |
2975d 22h |
/zipcpu/trunk/bench/ |
150 |
Minor changes. |
dgisselq |
2975d 22h |
/zipcpu/trunk/bench/ |
149 |
Updated the Makefile documentation and the all target. |
dgisselq |
2975d 22h |
/zipcpu/trunk/bench/ |
148 |
Minor changes to get LONG_MPY working, and adjust the documentation. |
dgisselq |
2975d 22h |
/zipcpu/trunk/bench/ |
147 |
Cleans up div_tb a bit, causing it to write SUCCESS out if successful and
abort if not. |
dgisselq |
2975d 22h |
/zipcpu/trunk/bench/ |
140 |
Minor changes, but fixes build of zippy_tb.cpp. |
dgisselq |
2979d 12h |
/zipcpu/trunk/bench/ |
134 |
Working updates, to keep this up to date with the RTL code. |
dgisselq |
2996d 23h |
/zipcpu/trunk/bench/ |
105 |
Fixed some nasty early branching bugs. Adjusted the Makefile to declare that
cpudefs.h was automatically generated from cpudefs.v, and made sure that
zipbones included the cpudefs.v so it could get the DEBUG_SCOPE define.
In addition, the test.S was updated to test long jumps, the early branching
bug we found, and all three early branching instructions: ADD #x,PC, LOC(PC),PC,
and LDI #x,PC. |
dgisselq |
3040d 08h |
/zipcpu/trunk/bench/ |
87 |
Adjusted the operator input line to reflect actual logic inputs, rather
than the registered inputs which may have been out of date. (Indeed, they
were out of date for the bug I was chasing and fixed ...) |
dgisselq |
3107d 00h |
/zipcpu/trunk/bench/ |
86 |
Removed the requirement to have the dev.scope.cpu hardware defined outside
of the Zip CPU (it was defined in another project). This was causing a bus
error in the simulator (which it should have), but taking it out fixes things
in the simulator (while removing capability from one special piece of H/W). |
dgisselq |
3107d 00h |
/zipcpu/trunk/bench/ |
77 |
First check-in: the test bench for the divide instruction. |
dgisselq |
3112d 03h |
/zipcpu/trunk/bench/ |
76 |
The biggest change here was to zippy_tb, to make it more similar to the debugger
and to make it work with VLIW-type instructions. |
dgisselq |
3112d 03h |
/zipcpu/trunk/bench/ |
75 |
Modified for VLIW instructions. |
dgisselq |
3112d 03h |
/zipcpu/trunk/bench/ |
74 |
Added a bunch of debugging code to the Dhrystone benchmark assembly file, as
well as two new testing assembly files. |
dgisselq |
3112d 03h |
/zipcpu/trunk/bench/ |
69 |
This implements the "new Instruction Set" architecture for the Zip CPU. It's
a massive change set, that touches just about everything but probably not
enough of everything. Please see the spec.pdf for a description of this
new architecture. |
dgisselq |
3118d 08h |
/zipcpu/trunk/bench/ |