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Rev Log message Author Age Path
351 Turn defines into parameters in eth_cop olof 4706d 19h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4706d 19h /
349 Make all parameters configurable from top level olof 4707d 20h /
348 Added option to dump VCD files olof 4708d 19h /
347 Added information about running with Icarus Verilog olof 4708d 19h /
346 Updated project location olof 4708d 21h /
345 Temporarily disable failing tests olof 4708d 23h /
344 bit 9 in phy control register is self clearing olof 4715d 01h /
343 Address miss should not be asserted on short frames olof 4718d 21h /
342 Added cast to avoid inequality when comparing different data types olof 4718d 21h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4718d 21h /
340 Don't fail if log dir already exists olof 4719d 19h /
339 Added basic support for Icarus Verilog olof 4720d 18h /
338 root 5513d 00h /
337 root 5569d 02h /
336 Added old uploaded documents to new repository. root 5570d 05h /
335 New directory structure. root 5570d 05h /
334 Minor fixes for Icarus simulator. igorm 7018d 07h /
333 Some small fixes + some troubles fixed. igorm 7018d 19h /
332 Case statement improved for synthesys. igorm 7032d 00h /

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