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Subversion Repositories ethmac10g

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Rev Log message Author Age Path
74 Added old uploaded documents to new repository. root 5568d 20h /
73 Added old uploaded documents to new repository. root 5569d 12h /
72 New directory structure. root 5569d 12h /
71 Replay xilinx fifo with private fifo fisher5090 5903d 09h /
70 no message fisher5090 6567d 03h /
69 no message fisher5090 6567d 03h /
68 datasheet of management module fisher5090 6567d 14h /
67 modify mgmt_miim_rdy timing sequence fisher5090 6567d 21h /
66 comments added fisher5090 6568d 01h /
65 bad coding style, but works, will be modified later fisher5090 6568d 04h /
64 no message fisher5090 6570d 15h /
63 remove pad function added, using xilinx vp20 -6 as target FPGA, passes post place and route simulation fisher5090 6570d 15h /
62 no message fisher5090 6570d 21h /
61 no message fisher5090 6570d 23h /
60 change rxd_in, rxc_in and rxclk_in signals'name to xgmii_rxd, xgmii_rxc and xgmii_rxclk fisher5090 6570d 23h /
59 first version fisher5090 6571d 00h /
58 configuration vector select inband fcs or not fisher5090 6571d 05h /
57 both inband fcs and no inband fcs are OK fisher5090 6571d 05h /
56 no message fisher5090 6571d 21h /
55 testbench for normal frame and error frame fisher5090 6571d 22h /

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