URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] - Rev 82

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
82	added first version of axi-lite interface and testbench for basic axi-lite operations, now under test	JonasDC	4087d 10h	/
81	updated files, now using the components of the mod_sim_exp_pkg instead of direct entity declaration	JonasDC	4087d 10h	/
80	renamed to version 1.1 to follow the versioning system	JonasDC	4097d 04h	/
79	Tag for version 1.3 (with new ram style	JonasDC	4097d 04h	/
78	updated documentation with new RAM style information	JonasDC	4097d 04h	/
77	found fault in code, now synthesizes normally	JonasDC	4103d 02h	/
76	testbench update	JonasDC	4105d 13h	/
75	made rw_address a vector of a fixed width	JonasDC	4105d 13h	/
74	removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented.	JonasDC	4108d 09h	/
73	updated plb interface, mem_style and device generics added	JonasDC	4109d 08h	/
72	deleted old resources	JonasDC	4110d 08h	/
71	added synthesis report for altera and xilinx for the new ram. added coregen sources for xilinx for primitive RAM	JonasDC	4110d 08h	/
70	updated testbench for use with new core parameters updated makefile, added new sources	JonasDC	4110d 08h	/
69	big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources.	JonasDC	4110d 08h	/
68	branch no longer needed	JonasDC	4110d 10h	/
67	added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring.	JonasDC	4110d 11h	/
66	added asymmetric ram structures to support a more performant ramstyle. defined for xilinx and altera, not tested with other tools.	JonasDC	4110d 12h	/
65	updated plb interface, now modulus is selectable and, fifo depth is adjustable. updated makefile with new sources and update component in package	JonasDC	4118d 03h	/
64	added synthesis reports of xilinx and altera	JonasDC	4118d 09h	/
63	now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx	JonasDC	4118d 09h	/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories mod_sim_exp

[/] - Rev 82

Filtering Options