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Rev Log message Author Age Path
991 Different memory controller. simons 7992d 09h /
990 Test is now complete. simons 7992d 09h /
989 c++ is making problems so, for now, it is excluded. simons 7993d 17h /
988 ORP architecture supported. simons 7994d 08h /
987 ORP architecture supported. simons 7994d 16h /
986 outputs out of function are not registered anymore markom 7994d 16h /
985 DTLB translation doesn't work on or1ksim when IC/DC enabled. lampret 7995d 04h /
984 Disable SB until it is tested lampret 7995d 04h /
983 First checkin lampret 7995d 06h /
982 Moved to sim/bin lampret 7995d 06h /
981 First checkin. lampret 7995d 06h /
980 Removed sim.tcl that shouldn't be here. lampret 7995d 06h /
979 Removed old test case binaries. lampret 7995d 06h /
978 Added variable delay for SRAM. lampret 7995d 06h /
977 Added store buffer. lampret 7995d 06h /
976 Added store buffer lampret 7995d 06h /
975 First checkin lampret 7995d 06h /
974 Enabled what works on or1ksim and disabled other tests. lampret 7995d 08h /
973 generated cuc top scheduler builds without syntax errors; not tested yet markom 7997d 12h /
972 Interrupt suorces fixed. simons 7997d 13h /

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