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Rev Log message Author Age Path
74 This commit was manufactured by cvs2svn to create tag 'rel_3'. 7829d 04h /
73 Bug fixes, testcases added. mihad 7829d 04h /
72 *** empty log message *** mihad 7876d 08h /
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.
mihad 7884d 00h /
70 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7921d 07h /
69 Changed BIST signal names etc.. mihad 7921d 07h /
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7924d 17h /
67 Changed BIST signals for RAMs. tadejm 7924d 21h /
66 Changed empty status generation in pciw_fifo_control.v mihad 7928d 08h /
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7931d 06h /
64 The testcase I just added in previous revision repaired mihad 7931d 08h /
63 Added additional testcase and changed rst name in BIST to trst mihad 7931d 10h /
62 Added BIST signals for RAMs. mihad 7934d 03h /
61 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7942d 03h /
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7942d 03h /
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7942d 04h /
58 Removed all logic from asynchronous reset network mihad 7947d 04h /
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7947d 10h /
56 Number of state bits define was removed mihad 7948d 01h /
55 Changed state machine encoding to true one-hot mihad 7948d 02h /

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