URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] - Rev 135

Rev	Log message	Author	Age	Path
115	change uart to meet timing.	simont	7770d 23h	/
114	remove t2mod register	simont	7774d 02h	/
113	signal prsc_ow added.	simont	7774d 02h	/
112	change timers to meet timing specifications (add divider with 12)	simont	7774d 02h	/
111	Remove instruction cache and wb_interface	simont	7774d 17h	/
110	change adr_i and adr_o length.	simont	7774d 17h	/
109	add `include "oc8051_defines.v"	simont	7774d 17h	/
108	fix some bugs, use oc8051_cache_ram.	simont	7774d 17h	/
107	Include instruction cache.	simont	7774d 18h	/
106	generic_dpram used	simont	7775d 20h	/