URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] - Rev 80

Rev	Log message	Author	Age	Path
60	Bug fix; removed a combinational loop from the a25_decode logic.	csantifort	4567d 22h	/
59	Added modelsim script for reloading a wlf file after a simulation has been rerun.	csantifort	4637d 20h	/
58	Use TB.clk_count for the decompiler messages and removed the local counter	csantifort	4637d 23h	/
57	Add some debug messages	csantifort	4637d 23h	/
56	Remove the timeouts file from svn. Its an output file and gets now just gets created automatically when sims are run for the first time.	csantifort	4637d 23h	/
55	Added sudo to rm mnt command	csantifort	4637d 23h	/
54	Bug fix for bug reported by Botao Lee. The mode bits in the decode stage did not change immediately after a mode switch from a teqp instruction, but 1 cycle later. This meant the wrong set of registers was selected for writing to for 1 clock cycle.	csantifort	4654d 23h	/
53	Cleaned up Amber Verilog, removing unused signals.	csantifort	4669d 21h	/
52	Fixed typo in notes on creating DDR memory interfaces using coregen	csantifort	4669d 21h	/
51	Revert vmlinux back to 48.	csantifort	4710d 21h	/