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[/] - Rev 146

Rev	Log message	Author	Age	Path
126	Error counters fixed to be compatible with Bosch VHDL reference model. Small synchronization changes.	mohor	7557d 11h	/
125	Synchronization changed, error counters fixed.	mohor	7561d 17h	/
124	ALTERA_RAM supported.	mohor	7581d 23h	/
123	This commit was manufactured by cvs2svn to create tag 'rel_17'.		7589d 05h	/
122	This commit was manufactured by cvs2svn to create tag 'rel_16'.		7589d 05h	/
121	When detecting bus-free, signal bus_free_cnt_en was cleared to zero although the last sampled bit was zero instead of one.	mohor	7589d 05h	/
120	This commit was manufactured by cvs2svn to create tag 'rel_15'.		7598d 02h	/
119	Artisan RAMs added.	mohor	7598d 02h	/
118	Artisan RAM fixed (when not using BIST).	mohor	7598d 02h	/
117	Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need to be joined together on higher level.	mohor	7598d 02h	/