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[/] - Rev 71

Rev	Log message	Author	Age	Path
51	Xilinx RAM added.	mohor	7804d 13h	/
50	Top level signal names changed.	mohor	7804d 13h	/
49	Actel APA ram changed. Now synchronous read is used.	mohor	7808d 04h	/
48	Actel APA ram supported.	mohor	7808d 05h	/
47	Data is latched on read.	mohor	7808d 05h	/
46	This commit was manufactured by cvs2svn to create tag 'rel_1'.		7818d 03h	/
45	When a dominant bit was detected at the third bit of the intermission and node had a message to transmit, bit_stuff error could occur. Fixed.	mohor	7818d 03h	/
44	When bit error occured while active error flag was transmitted, counter was not incremented.	mohor	7818d 04h	/
43	Directory keeper.	mohor	7818d 11h	/
42	Initial version of the project.	mohor	7818d 11h	/