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[/] - Rev 78

Rev	Log message	Author	Age	Path
58	timescale.v is used for simulation only.	mohor	7819d 02h	/
57	Mux used for clkout to avoid "gated clocks warning".	mohor	7819d 02h	/
56	Doubled declarations removed.	mohor	7820d 00h	/
55	wire declaration added.	mohor	7820d 01h	/
54	This commit was manufactured by cvs2svn to create tag 'branch-release-1-0'.		7825d 02h	/
53	CAN pins located.	mohor	7825d 02h	/
52	tx_o is now tristated signal. tx_oen and tx_o combined together.	mohor	7825d 02h	/
51	Xilinx RAM added.	mohor	7825d 03h	/
50	Top level signal names changed.	mohor	7825d 03h	/
49	Actel APA ram changed. Now synchronous read is used.	mohor	7828d 19h	/