URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] - Rev 39

Rev	Log message	Author	Age	Path
19	Wishbone data latched on wb_clk_i instead of risc_clk.	mohor	8274d 11h	/
18	Reset signals are not combined any more.	mohor	8276d 20h	/
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8300d 09h	/
16	bs_chain_o port added.	mohor	8302d 09h	/
15	bs_chain_o added.	mohor	8302d 10h	/
14	Document updated.	mohor	8303d 08h	/
13	Signal names changed to lowercase.	mohor	8303d 11h	/
12	Wishbone interface added, few fixes for better performance, hooks for boundary scan testing added.	mohor	8304d 11h	/
11	Changes connected to the OpenRISC access (SPR read, SPR write).	mohor	8325d 07h	/
10	First official release 1.0.	mohor	8329d 10h	/