URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] - Rev 78

Rev	Log message	Author	Age	Path
58	This commit was manufactured by cvs2svn to create tag 'rel_3'.		7637d 13h	/
57	Multiple cpu support added.	simons	7637d 13h	/
56	Revision 1.6. Trst changed to active high !!!. In order to be compliant with the standard, reset needs to be negated on the upper layer.	mohor	7904d 09h	/
55	Revision 1.6. Trst changed to active high !!!. In order to be compliant with the standard, reset needs to be negated on the upper layer.	mohor	7904d 10h	/
54	This commit was manufactured by cvs2svn to create tag 'rel_2'.		7904d 11h	/
53	Trst active high. Inverted on higher layer.	mohor	7904d 11h	/
52	Trst signal is not inverted here any more. Inverted on higher layer !!!.	mohor	7904d 11h	/
51	WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated.	mohor	7931d 23h	/
50	Revision 1.5 of the document ready. WISHBONE Scan Chain changed.	mohor	7931d 23h	/
49	This commit was manufactured by cvs2svn to create tag 'sdram_test_working'.		8087d 11h	/