URL https://opencores.org/ocsvn/m1_core/m1_core/trunk

Subversion Repositories m1_core

[/] - Rev 47

Rev	Log message	Author	Age	Path
27	Corrected problems with synthesis and removed system control registers	fafa1971	5779d 07h	/
26	Changed blocking / non-blocking assignments for MUL and DIV requests	fafa1971	5779d 08h	/
25	For now the top-level for synthesis is just m1_cpu	fafa1971	5779d 08h	/
24	Corrected include dirs	fafa1971	5779d 08h	/
23	New script using the correct command file for synthesis with Xilinx ISE WebPack	fafa1971	5779d 08h	/
22	Added script file for synthesis with Xilinx ISE WebPack	fafa1971	5779d 08h	/
21	First revision (you should substitute '~' char with real path).	fafa1971	5786d 01h	/
20	Used only lower bits also for SRAV instruction.	fafa1971	5804d 13h	/
19	Added changes suggested by Paolo Piscopo & Simone Lunardo to fix the bugs they found.	fafa1971	5814d 09h	/
18	Limited range of SHAMT (shift amount) to be only 5 bits ([4:0])	fafa1971	5814d 09h	/