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Rev Log message Author Age Path
42 Added backpressure/stallability of output interface. mikel262 5348d 01h /
41 Fixed RLE ZRL bug occurring at end of 8x8 block mikel262 5485d 13h /
40 Fixed few bugs in BUF_FIFO and RLE encoder. mikel262 5528d 04h /
39 bug fix. mikel262 5531d 02h /
38 Reduced processing latency of Huffman encoding mikel262 5556d 02h /
37 Replaced VHDL Header RAM with Verilog, initialized via readmemh from hex file. mikel262 5560d 06h /
36 Fixed RLE ZRL bug. Added Chrominance Huffman tables. Fixed num encoded bytes bug. mikel262 5562d 02h /
35 Added check for image width in testbench. mikel262 5562d 14h /
34 Moved Quantizer to separate pipeline stage to balance processing chain load. mikel262 5562d 23h /
33 mikel262 5563d 07h /

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