URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] - Rev 229

Rev	Log message	Author	Age	Path
209	Fixed an issue in the PIT timer that caused an immediate interrupt on interval write, Fixed an issue in the epoch timer that resulted in a spurious interrupt due to extra LSB's being set by default in the set point register, While cleaning elsewhere, founding a spacing issue in the CPU HDL, Added a 4k ROM and MW core.	jshamlet	1567d 01h	/
208	Removed unnecessary package references	jshamlet	1567d 10h	/
207	Added a simple 8-bit, fixed asynchronous serial interface with compile time settable bit-rate, parity enable, and parity mode generics.	jshamlet	1568d 03h	/
206	Merged interrupt logic with other clocked process.	jshamlet	1571d 22h	/
205	More code and comment cleanup for the new SDLC engine	jshamlet	1571d 22h	/
204	Fixed more incorrect comments	jshamlet	1571d 23h	/
203	Removed an extra delay FF from the bitclock rising edge signal for the clock slave configuration to better center the rising edge pulse on the receive signal.	jshamlet	1572d 05h	/
202	Fixed receiver bug that caused false flag detection, Split the large sdlc_serial_ctrl entity into sub-entities to make debugging easier.	jshamlet	1572d 06h	/
201	Fixed comments regarding RX Checksum location	jshamlet	1574d 03h	/
200	Renamed dual-port buffer to match other entities.	jshamlet	1574d 03h	/