OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] - Rev 302

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
282 Modified the SDLC core transmit states to have consistent naming. jshamlet 1352d 05h /
281 Added pre-initialization to the dual-port RAM signals. jshamlet 1352d 08h /
280 Got rid of silly aliases that connected the dual-port memory and the arbitration logic. jshamlet 1352d 09h /
279 More comment cleanup jshamlet 1353d 06h /
278 Flattened the SDLC interface to fewer files and eliminated the package file. jshamlet 1354d 00h /
277 Fixed documentation errors related to flags. The UPP ALU instruction only alters the C flag, not the Z or N flags. This implies that using indexed loads or stores with auto post-increment will potentially alter the C flag. jshamlet 1354d 06h /
276 More comment fixes jshamlet 1389d 02h /
275 Fixed a minor comment error. jshamlet 1390d 20h /
274 Updated comments with more corrections jshamlet 1391d 03h /
273 Updated comments with corrections jshamlet 1391d 05h /

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.