URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] - Rev 136

Rev	Log message	Author	Age	Path
116	Update documentation to reflect the latest core updates.	olivier.girard	4767d 15h	/
115	Add linker script example.	olivier.girard	4776d 15h	/
114	Improved the VerifyCPU_ID procedure.	olivier.girard	4779d 14h	/
113	Created ChangeLog files...	olivier.girard	4780d 14h	/
112	Modified comment.	olivier.girard	4784d 14h	/
111	Re-organized the "openMSP430_defines.v" file. Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning). Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000). As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.	olivier.girard	4785d 14h	/
110	Rework of the GUI for the software development tools. Added possibility to give custom information through the omsp_alias.xml file.	olivier.girard	4786d 14h	/
109	Update Xilinx FPGA example with the latest openMSP430 core RTL version.	olivier.girard	4839d 23h	/
108	Add serial debug interface tasks to the Actel fpga simulation environment.	olivier.girard	4841d 12h	/
107	Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version.	olivier.girard	4841d 12h	/