URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] - Rev 49

Rev	Log message	Author	Age	Path
29	Add Altera Cyclone II FPGA project example.	olivier.girard	5296d 19h	/
28	renamed "diligent_s3board" directory to "xilinx_diligent_s3board"	olivier.girard	5305d 02h	/
27	renamed "diligent_s3board" directory to "xilinx_diligent_s3board"	olivier.girard	5305d 02h	/
26	Xilinx implementation example: - update the project directory structure. - make a local copy of the openMSP430 core to make the project self contained.	olivier.girard	5305d 03h	/
25	FPGA Setup: Created some BAT files for WINDOWS users.	olivier.girard	5395d 00h	/
24	FPGA Setup: Created some BAT files for WINDOWS users.	olivier.girard	5395d 00h	/
23	Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file. In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).	olivier.girard	5415d 23h	/
22	Updated some links in the HTML documentation.	olivier.girard	5428d 20h	/
21	added discussion group info	olivier.girard	5440d 21h	/
20	added some SVN ignore patterns. small update to html documentation	olivier.girard	5441d 17h	/