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Rev Log message Author Age Path
62 Add Xilinx synthesis environment for size&speed analysis. olivier.girard 5291d 18h /
61 Update openMSP430 rtl. olivier.girard 5302d 06h /
60 Cleanup of the PC (R0) generation logic.
Formal equivalence was shown between the new and old code with Synopsys' Formality (to make sure that nothing has been broken :-P ).		 olivier.girard 5302d 07h /
59 Update the FPGA projects with the latest core design updates. olivier.girard 5304d 05h /
58 Update the debug hardware breakpoint verification patterns to reflect the latest design updates. olivier.girard 5304d 05h /
57 Update design to exclude the range mode from the debug hardware breakpoint units. As this feature is not used by GDB, it has been disabled in order to improve the timings and save a bit of area/utilisation.
Note that if required, this feature can be re-enabled through the `HWBRK_RANGE define located in the "openMSP430_defines.v" file.		 olivier.girard 5304d 05h /
56 Update Design Compiler Synthesis scripts. olivier.girard 5308d 12h /
55 Add a "sandbox" test pattern to play around with the simulation :-P olivier.girard 5309d 07h /
54 Update FPGA projects with the combinatorial loop fixed. olivier.girard 5309d 09h /
53 Fixed the following combinatorial timing loop:
1- irq_detect (omsp_frontend)
2- decode (omsp_frontend)
3- dbg_swbrk (omsp_dbg)
4- halt_flag_set (omsp_dbg)
6- dbg_halt_cmd (omsp_dbg)
7- irq_detect (omsp_frontend)

Without this fix, problem could occur whenever an IRQ request arrives during a software breakpoint instruction fetch.		 olivier.girard 5309d 10h /

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