URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] - Rev 134

Rev	Log message	Author	Age	Path
114	l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR.	jeremybennett	5124d 20h	/
113	Updates to exception handling for l.add and l.div	jeremybennett	5125d 18h	/
112	Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register.	jeremybennett	5125d 18h	/
111	Changed conditionals for Verilator to "verilator" instead of "VERILATOR".	jeremybennett	5125d 23h	/
110	or1ksim make check should work without a libc in the or32-elf tools	julius	5126d 20h	/
109	or_debug_proxy does signals with signals, just ignores signals	julius	5127d 04h	/
108	Updated to clarify overflow and exceptions for l.add, l.addc, l.addi, l.addic, l.div and l.divu.	jeremybennett	5128d 18h	/
107	New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug.	jeremybennett	5128d 19h	/
106	Removing old tests, pending addition of new ones.	jeremybennett	5128d 19h	/
105	Tagging the 0.4.0rc1 candidate release of Or1ksim	jeremybennett	5132d 02h	/