URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] - Rev 73

Rev	Log message	Author	Age	Path
53	Fixed incorrect commandline option for ORPSoC and main makefile setting	julius	5357d 07h	/
52	ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation	julius	5358d 03h	/
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5372d 05h	/
50	Adding or32_funcs.S	julius	5372d 10h	/
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5390d 23h	/
48	Adds an initialization to keep GCC happy in jp1_ll_read_jp1.	jeremybennett	5391d 02h	/
47	debug proxy speed increase, block transfers possible with cpu aslong as dbg_interface has appropriate change, usb chip reinit function, changed some of the retry code in the usb transfer functions	julius	5400d 10h	/
46	debug interfaces now support byte and non-aligned accesses from gdb	julius	5406d 11h	/
45	Orpsoc eth test fix and script error message update	julius	5413d 10h	/
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5442d 10h	/