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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

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Rev	Log message	Author	Age	Path
67	New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory	julius	5266d 14h	/
66	Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software.	julius	5286d 13h	/
65	ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix	julius	5290d 19h	/
64	Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile.	julius	5293d 14h	/
63	Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores.	julius	5303d 11h	/
62	This material is part of the separate website downloads directory.	jeremybennett	5314d 14h	/
61	The build directory should not be part of the SVN configuration.	jeremybennett	5314d 14h	/
60	Mark Jarvin's patches to support Mac OS X (Snow Leopard).	jeremybennett	5321d 08h	/
59	Toolchain install script gcc patch change and gdb configure change	julius	5342d 08h	/
58	ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up	julius	5345d 07h	/

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