URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] - Rev 451

Rev	Log message	Author	Age	Path
431	Updated and move OR1200 supplementary manual. or_debug_proxy GDB RSP interface fix. ORPSoC S/W and makefile updates.	julius	4998d 22h	/
430	or1ksim - clarifying interrupt behavior in code and documentation.	julius	4999d 20h	/
429	or1ksim update - remove debug printfs from eth MDIO emulation function and fix illegal instruction vector jump for invalid instructions.	julius	4999d 23h	/
428	or1ksim - adding preliminary PHY emulation to ethernet peripheral.	julius	5002d 19h	/
427	Fixes for C++ to correspond to fixes in uClibc.	jeremybennett	5004d 03h	/
426	ORPSoC update Reverted back to previous OR1200 instruction cache. (...which...) Fixed or1200-except test failure on generic model. ML501 build not passing or1200-except test. Tried disabling burst on the bus (memory server doesn't support it yet) to no avail. To be continued...	julius	5005d 14h	/
425	ORPSoC update: GDB servers in VPI and System C model updated to deal with packets gdb-7.2 sends. Documentation updated. Reference design tests can now be run in or1ksim (added rule to sim/bin/Makefile). or1200-except doesn't appear to work as illegal instruction error isn't causing jump to vector. Updated Or1200 tests to report test success value and then exit with value 0.	julius	5005d 15h	/
424	C++ library, needed for C++ compiler.	jeremybennett	5006d 01h	/
423	Minor typo fixed.	jeremybennett	5006d 04h	/
422	Separates out --force actions, so only build dirs corresponding to targets being built are blown away.	jeremybennett	5006d 04h	/