URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] - Rev 1161

Rev	Log message	Author	Age	Path
1141	WB = 1/2 RISC clock test code enabled.	lampret	7740d 18h	/
1140	Fixed OR1200_CLKDIV_x_SUPPORTED defines. Fixed order of ifdefs.	lampret	7740d 18h	/
1139	Fixed OR1200_CLKDIV_x_SUPPORTED defines. Better description.	lampret	7740d 18h	/
1138	Added some information how to run simulations.	lampret	7741d 13h	/
1137	Added RFRAM generic and Altera lpm library.	lampret	7741d 13h	/
1136	Add altera lpm library.	lampret	7741d 13h	/
1135	Added get_gpr support for OR1200_RFRAM_GENERIC	lampret	7741d 13h	/
1134	Changed location of debug test code to 0.	lampret	7741d 13h	/
1133	Adding OR1200_CLMODE_1TO2 test code.	lampret	7741d 13h	/
1132	RFRAM defines comments updated. Altera LPM option added.	lampret	7741d 13h	/