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Rev Log message Author Age Path
10 Ho ho, better circuit homer.xing 4525d 22h /
9 Add constrains file for ISE homer.xing 4527d 02h /
8 Finished Tate Pairing. Ha ha ha homer.xing 4527d 03h /
7 Finish inversion @ f33m homer.xing 4535d 08h /
6 add testbench for $f33m$. homer.xing 4536d 07h /
5 rename director : verilog/ -> rtl/ homer.xing 4536d 07h /
4 add testbench homer.xing 4537d 05h /
3 finish Duursma Lee algorithm. doing f33m module homer.xing 4537d 05h /
2 upload code for Duursma-Lee algorithm. I am still developing them. homer.xing 4538d 05h /
1 The project and the structure was created root 4538d 05h /

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