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Rev Log message Author Age Path
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7937d 02h /
67 Changed BIST signals for RAMs. tadejm 7937d 07h /
66 Changed empty status generation in pciw_fifo_control.v mihad 7940d 18h /
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7943d 16h /
64 The testcase I just added in previous revision repaired mihad 7943d 18h /
63 Added additional testcase and changed rst name in BIST to trst mihad 7943d 20h /
62 Added BIST signals for RAMs. mihad 7946d 13h /
61 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7954d 13h /
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7954d 13h /
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7954d 14h /

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