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Rev Log message Author Age Path
121 taking out std_logic_arith from sight.... no conversions allowed jguarin2002 4712d 15h /
120 Beta 0 Adder LCELLS 373 jguarin2002 4718d 13h /
119 382 LEs Adder, RTL viewer Check Ok jguarin2002 4718d 19h /
118 fp beta version reached a 17,5% logic cell starting at 450 LEs and finishing in 371 LEs for fadd32 jguarin2002 4719d 02h /
117 Official reduction achieved 12% jguarin2002 4719d 08h /
116 Official Reduction is 7%: Adder 420 logic cells, trying to reach out at least 20 less cells jguarin2002 4719d 09h /
115 Official Reduction is about 7% jguarin2002 4719d 09h /
114 lost of time.. jguarin2002 4720d 08h /
113 Will end this tomorrow for sure.... anyway i dont think i will got something below 400... jguarin2002 4725d 22h /
112 99.7%... almost there jguarin2002 4726d 00h /

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