URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] - Rev 44

Rev	Log message	Author	Age	Path
24	4k Data Instruction for Spartan 3 (Block RAM) Added write enable to the entity	ustadler	6417d 08h	/
23	4k Data Memory for Spartan 3 (Block RAM) Added write enable to the entity	ustadler	6417d 08h	/
22	testbench für die register file	ustadler	6417d 22h	/
21	überarbeitet. asynchrones lesen und synchrones schreiben. dreg_enable, sr_enable und lr_enable zur entity hinzugefügt	ustadler	6418d 09h	/
20	- Fixed bug where SR fetch code locked wrong register.	cwalter	6418d 11h	/
19	Version 1.2 der register file	ustadler	6418d 19h	/
18	Update of pipeline schematics: - Fixed errors - Changed names of some signals so they are equal with VHDL code - Added second register lock port	jlechner	6419d 14h	/
17	- Added new tests for pipeline stall signal. - Added tests for register locking. - Added tests for OPCODE_ST_DISP, OPCODE_ADD, OPCODE_ADD_IMM OPCODE_SUB_IMM, OPCODE_NEG, OPCODE_ARS and OPCODE_ALS.	cwalter	6421d 11h	/
16	- Added second register locking port reg_lock1 to RLU.	cwalter	6421d 11h	/
15	- Added second register locking port reg_lock1. - Added function to check if the instruction modifies the SR register. - Fetch of SR now checks if the SR is modified and if yes the SR register is marked as locked. - Stall signal for pipeline is now generated correctly. - Stall input is now checked. If asserted the current output values are hold until the stall signal is deasserted.	cwalter	6421d 11h	/