URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] - Rev 67

Rev	Log message	Author	Age	Path
47	SDRAM bus converter bug fix and top-level signal clean up	dinesha	4506d 18h	/
46	test bench upgrade + rtl cleanup	dinesha	4508d 18h	/
45	RTL clean up and logic seperation done from sdram bus converter and request generator	dinesha	4508d 23h	/
44	SDRAM data path logic is modified to support 4 command line pipe line of different bank	dinesha	4510d 21h	/
43	Test bench automation to handle differ write/read burst sequence is supported now	dinesha	4510d 22h	/
42	Bug fix in read access is fixed	dinesha	4510d 23h	/
41	Updated Spec ver 0.1 is added back to svn	dinesha	4511d 00h	/
40	Application layer Fifo full conditional are register now to synth timing fixes	dinesha	4511d 17h	/
39	Test Bench upgradation with bigger data burst size	dinesha	4511d 17h	/
38	Port Name clean up	dinesha	4512d 22h	/