URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] - Rev 97

Rev	Log message	Author	Age	Path
77	now generate syn and cov Makefiles leave log and out files in sim/run directory	jt_eaton	5019d 14h	/
76	added wave.save files now generate sims Makefile and params.sim leave sim log and vcd files in sim/run/directory	jt_eaton	5021d 19h	/
75	added linting using verilator	jt_eaton	5025d 11h	/
74	split out sw Makefile into projects /bin split out _cpu into seperate component	jt_eaton	5030d 17h	/
73	removed dup png files	jt_eaton	5038d 16h	/
72	split T6502 into components moved io_module into seperate project removed liblists direct loads filelists for sims and coverage add hier type into xml files to generate verilog	jt_eaton	5038d 18h	/
71	ignore anything in work	jt_eaton	5045d 11h	/
70	ignore work	jt_eaton	5045d 11h	/
69	added work dir	jt_eaton	5045d 11h	/
68	moved to seperate components	jt_eaton	5048d 11h	/