URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] - Rev 100

Rev	Log message	Author	Age	Path
80	Grouping some instructions that have the same behavioral.	gabrieloshiro	5622d 15h	/
79	ALU testbench added.	gabrieloshiro	5622d 16h	/
78	ZPG coded and simulated.	creep	5622d 16h	/
77	ZPG coded. Simulation is halfway.	creep	5622d 17h	/
76	ABS write instructions were not simulated. Also added some initial ZPG simulation.	creep	5622d 17h	/
75	First working version!	gabrieloshiro	5622d 17h	/
74	The file now describes who is doing what.	creep	5622d 18h	/
73	Added schedule file into the readme file.	creep	5622d 18h	/
72	Project management folder.	creep	5622d 18h	/
71	Four addressing modes are simulated: immediate, accumulator, implied and absolute. The simulation was done using a testbench that contains a small memory inside.	creep	5622d 18h	/