URL https://opencores.org/ocsvn/tinycpu/tinycpu/trunk

Subversion Repositories tinycpu

[/] - Rev 37

Rev	Log message	Author	Age	Path
17	Added fetch component for fetching from memory to instruction register Added additional testing for carryover to make sure it's correct	earlz	4424d 23h	/
16	Renamed incdec to carryover (see design for why). carryover should be done, though may change the "straight through on disable" behavior to instead leaving it floating depending on how things go later with coding.	earlz	4428d 01h	/
15	Added README, LICENSE, and the (so far not created) incdec component	earlz	4429d 23h	/
14	Added ALU with all the operations we'll need. Synthesizes as well trivially	earlz	4430d 07h	/
13	Forgot about the new library I added	earlz	4430d 09h	/
12	registerfile has ports for every register now makefile now uses GHW file format for gtkwave instead of VCD	earlz	4430d 10h	/
11	Finally, it synthesizes to BRAM.. Possibly need to fix how the DataOut syncs with WriteEnable and Address though if I plan to both read and write on the same clock edge	earlz	4434d 00h	/
10	Just committing so I can keep this original that passes simulation, but still synthesizes to LUTs	earlz	4434d 00h	/
9	Trying to add a byte-enable to the RAM. Used Xilinx's template for it, but ghdl won't pass the testbench	earlz	4434d 08h	/
8	Added blockram for inferring actual block RAM. Now we need a memory controller, not a crappy memory emulation thing	earlz	4435d 07h	/