URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] - Rev 73

Rev	Log message	Author	Age	Path
53	Scratch register define added.	mohor	8248d 08h	/
52	Scratch register added	gorban	8248d 21h	/
51	Igor fixed break condition bugs	gorban	8248d 21h	/
50	Bug in LSR[0] is fixed. All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.	gorban	8253d 02h	/
49	committed the debug interface file	gorban	8254d 19h	/
48	Updated specification documentation. Added full 32-bit data bus interface, now as default. Address is 5-bit wide in 32-bit data bus mode. Added wb_sel_i input to the core. It's used in the 32-bit mode. Added debug interface with two 32-bit read-only registers in 32-bit mode. Bits 5 and 6 of LSR are now only cleared on TX FIFO write. My small test bench is modified to work with 32-bit mode.	gorban	8255d 19h	/
47	Fixed: timeout and break didn't pay attention to current data format when counting time	gorban	8260d 21h	/
46	Fixed bug that prevented synthesis in uart_receiver.v	gorban	8261d 18h	/
45	Lots of fixes: Break condition wasn't handled correctly at all. LSR bits could lose their values. LSR value after reset was wrong. Timing of THRE interrupt signal corrected. LSR bit 0 timing corrected.	gorban	8262d 19h	/
44	fixed more typo bugs	gorban	8276d 19h	/