URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] - Rev 101

Rev	Log message	Author	Age	Path
81		mikaeljf	5131d 10h	/
80		mikaeljf	5131d 11h	/
79	Added defines that fix bugs with slow wishbone clocks doing burst writes	julius	5169d 01h	/
78	Burst writing working again, although its mostly hardcoded to burst 4. Also added a fix for when the RAM and bus clocks are about the same speed, to avoid buffer overrun	julius	5171d 08h	/
77	SDR 16 registering of current_fifo_empty signal in top, appropriate control alterations in fsm_sdr_16	julius	5179d 06h	/
76	Changed SDR16 synthesis useioff location, fsm_wb acking logic, default SDR build is for 16m part now	julius	5184d 07h	/
75		mikaeljf	5184d 08h	/
74	Minor update of rtl Makefile.	mikaeljf	5188d 07h	/
73	Minor updates to fix lost revisions 69 and 70.	mikaeljf	5188d 08h	/
72	Restored lost revisions 69 and 70.	mikaeljf	5188d 09h	/