URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] - Rev 46

Rev	Log message	Author	Age	Path
26	compiles OK, not simulated	unneback	5275d 01h	/
25		unneback	5275d 04h	/
24	Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions.	mikaeljf	5275d 15h	/
23	Removed redundant code.	mikaeljf	5283d 08h	/
22	Updated the Altera timing constraints file, also minor updates of defines file and Makefile.	mikaeljf	5285d 04h	/
21	Updated the Altera timing constraints file (.sdc).	mikaeljf	5289d 07h	/
20	Minor update of sdc-file.	mikaeljf	5291d 08h	/
19	Added do-file for Modelsim waveform viewer.	mikaeljf	5297d 13h	/
18	Updated the rtl/verilog Makefile and the bench Makefile.	mikaeljf	5298d 10h	/
17	Modified rtl Makefile and tb_defines.v	mikaeljf	5301d 09h	/