URL https://opencores.org/ocsvn/vga_lcd/vga_lcd/trunk

Subversion Repositories vga_lcd

[/] - Rev 40

Rev	Log message	Author	Age	Path
20	Switched parameter order.	rherveille	8338d 05h	/
19	Major revisions throughout the core. Moved Color Lookup Table inside core. Changed control & status register contents. Changed port names to be conform to new naming convention. Fixed bug in CAB assertion. Changed video memory address generation. and many more ....	rherveille	8338d 06h	/
18	Removed files. They are not used anymore.	rherveille	8367d 04h	/
17	Major rework. Included generic memory models. Core now supports pixel clocks at same speed as wishbone clock (except for 8bpp color mode)	rherveille	8367d 04h	/
16	- Changed Directory Structure - Added verilog Source Code - Changed IO pin names and defines statements	rudi	8394d 10h	/
15	Created directory structure (documentation, vhdl, verilog)	rherveille	8430d 00h	/
14	Added CLUT bank switching. Replaced multiplier with simple counters. Fixed timing bug.	rherveille	8430d 19h	/
13	Replaced csm.vhd by csm_pb.vhd. Core does not require CLKx2 clock anymore.	rherveille	8431d 07h	/
12	Added new top-level and sub-level (vga_and_clut.vhd & csm.vhd); adds color-lookup-table to the VGA core (i.e. on-chip CLUT). Ram generation has been tested with Altera and Xilinx parts.	rherveille	8440d 11h	/
11	Major bug fixes in Wishbone Master and ColorProcessor blocks. Core did not respond correctly to delayed ACK_I signals. Added built-in Color Lookup Tables.	rherveille	8440d 11h	/