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Rev Log message Author Age Path
54 complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module. rehayes 5295d 15h /
53 Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal. rehayes 5295d 15h /
52 Minor changes to aide waveform debug rehayes 5295d 15h /
51 Corrections to ADC and SBC instructions, First pass at documentaion instruction set details rehayes 5311d 11h /
50 incremental update to match status bit changes rehayes 5311d 11h /
49 First pass with instruction set details rehayes 5311d 11h /
48 Update for SBC ana ADC condition code changes rehayes 5311d 12h /
47 Fix status bit error in ADC and SBC instruction, fix error in thread startup. rehayes 5311d 12h /
46 Update to remove stack registers and add new register text. rehayes 5343d 10h /
45 Update to remove stack registers and add new register text. rehayes 5343d 10h /

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