URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] - Rev 86

Rev	Log message	Author	Age	Path
66	Fix testbench and RISC core related to debug mode and wait states.	rehayes	5213d 06h	/
65	Parameterize delays based on number of RAM wait states.	rehayes	5213d 06h	/
64	Fixed more bugs related to wait states and debug mode.	rehayes	5213d 06h	/
63	Remove historical output ports that are no longer used.	rehayes	5223d 05h	/
62	Cleanup implicit wire declarations.	rehayes	5223d 05h	/
61	Update to RISC block to fix DEBUG mode, testbench update	rehayes	5230d 05h	/
60	Add ability at insert wait states on RAM access	rehayes	5230d 05h	/
59	Fix bug in entering DEBUG mode from WB bus command	rehayes	5230d 05h	/
58	WISHBONE Bus update.	rehayes	5282d 05h	/
57	Traded 16 data registers for 5 address regester when wait states are enabled.	rehayes	5282d 08h	/