URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] - Rev 76

Rev	Log message	Author	Age	Path
56	Brings code in line with the OpenCores core: parameterizes the reload value, and the number of bits in the timer.	dgisselq	2942d 04h	/
55	Updated copyright notice.	dgisselq	2942d 04h	/
54	Updated copyright notice.	dgisselq	2942d 04h	/
53	Added a touch of error checking.	dgisselq	2982d 04h	/
52	This brings the XuLA2-LX25 SoC up to speed with the rest of the ZipCPU, and prepares it for the 32x32 bit multiply instruction set change.	dgisselq	2982d 04h	/
51	Lots of bug fixes. The ugliest were in the prefetch cache, where instructions from one cache line were being issued as valid in another. Other fixes include pipeline fixes so that LOD (Rx),Rx; LOD(Rx),Rx works, and more. Finally, the decode was adjusted so that brev no longer affects the flags.	dgisselq	2992d 02h	/
50	Updates to fix some broken early branching code, both in idecode and pfcache.	dgisselq	3001d 05h	/
49	Added some documentation to make the read and write calls easier to understand.	dgisselq	3010d 05h	/
48	Cleaned up the documentation a touch. It no longer reads like the bugs I used to debug are still being debugged ...	dgisselq	3012d 07h	/
47	Fixes the "NAN" clocks/second output, as well as making input timing come closer to a realistic timing. (I actually don't know what timing the JTAG port is providing, but ... the new timer is closer.)	dgisselq	3012d 07h	/