URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] - Rev 78

Rev	Log message	Author	Age	Path
58	Bug fix: the UART can now be reconfigured post-boot without a BREAK condition.	dgisselq	2948d 02h	/
57	Fixed the TX/RX addresses so that they match the documentation: TX first, then RX.	dgisselq	2956d 02h	/
56	Brings code in line with the OpenCores core: parameterizes the reload value, and the number of bits in the timer.	dgisselq	2956d 02h	/
55	Updated copyright notice.	dgisselq	2956d 02h	/
54	Updated copyright notice.	dgisselq	2956d 02h	/
53	Added a touch of error checking.	dgisselq	2996d 02h	/
52	This brings the XuLA2-LX25 SoC up to speed with the rest of the ZipCPU, and prepares it for the 32x32 bit multiply instruction set change.	dgisselq	2996d 02h	/
51	Lots of bug fixes. The ugliest were in the prefetch cache, where instructions from one cache line were being issued as valid in another. Other fixes include pipeline fixes so that LOD (Rx),Rx; LOD(Rx),Rx works, and more. Finally, the decode was adjusted so that brev no longer affects the flags.	dgisselq	3006d 01h	/
50	Updates to fix some broken early branching code, both in idecode and pfcache.	dgisselq	3015d 03h	/
49	Added some documentation to make the read and write calls easier to understand.	dgisselq	3024d 03h	/