URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] - Rev 166

Rev	Log message	Author	Age	Path
145	fix bug in case of sequence of inc dptr instrucitons.	simont	7732d 22h	/8051/tags/rel_12/
144	chsnge comp.des to des1	simont	7732d 22h	/8051/tags/rel_12/
143	add wire sub_result, conect it to des_acc and des1.	simont	7732d 22h	/8051/tags/rel_12/
142	optimize state machine.	simont	7733d 23h	/8051/tags/rel_12/
141	remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.	simont	7734d 01h	/8051/tags/rel_12/
140	cahnge assigment to pc_wait (remove istb_o)	simont	7734d 01h	/8051/tags/rel_12/
139	add aditional alu destination to solve critical path.	simont	7734d 19h	/8051/tags/rel_12/
138	Change buffering to save one clock per instruction.	simont	7734d 19h	/8051/tags/rel_12/
137	change to fit xrom.	simont	7735d 00h	/8051/tags/rel_12/
136	registering outputs.	simont	7735d 00h	/8051/tags/rel_12/