URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] - Rev 122

Rev	Log message	Author	Age	Path
93	OC8051_XILINX_RAM added	simont	7799d 12h	/8051/tags/rel_12/rtl/verilog/
92	initial inport	simont	7799d 12h	/8051/tags/rel_12/rtl/verilog/
90	change module name.	simont	7804d 06h	/8051/tags/rel_12/rtl/verilog/
89	Replaced oc8051_ram by generic_dpram.	rherveille	7865d 09h	/8051/tags/rel_12/rtl/verilog/
88	fix bugs	simont	7870d 09h	/8051/tags/rel_12/rtl/verilog/
87	add include oc8051_defines.v	simont	7870d 09h	/8051/tags/rel_12/rtl/verilog/
82	replace some modules	simont	7878d 09h	/8051/tags/rel_12/rtl/verilog/
81	initial import	simont	7878d 09h	/8051/tags/rel_12/rtl/verilog/
80	removing unused modules	simont	7878d 09h	/8051/tags/rel_12/rtl/verilog/
78	alu with registered outputs	simont	7938d 09h	/8051/tags/rel_12/rtl/verilog/