URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] - Rev 151

Rev	Log message	Author	Age	Path
127	fix bug (cyc_o and stb_o)	simont	7763d 02h	/8051/tags/rel_12/rtl/verilog/
126	define OC8051_XILINX_RAMB added	simont	7763d 02h	/8051/tags/rel_12/rtl/verilog/
123	fiz bug iv pcs operation.	simont	7764d 21h	/8051/tags/rel_12/rtl/verilog/
122	deifne OC8051_ROM added	simont	7768d 01h	/8051/tags/rel_12/rtl/verilog/
121	Change pc add value from 23'h to 16'h	simont	7768d 01h	/8051/tags/rel_12/rtl/verilog/
120	defines for pherypherals added	simont	7768d 23h	/8051/tags/rel_12/rtl/verilog/
119	remove signal sbuf_txd [12:11]	simont	7769d 03h	/8051/tags/rel_12/rtl/verilog/
118	change wr_sft to 2 bit wire.	simont	7769d 19h	/8051/tags/rel_12/rtl/verilog/
117	Register oc8051_sfr dato output, add signal wait_data.	simont	7769d 20h	/8051/tags/rel_12/rtl/verilog/
116	change sfr's interface.	simont	7771d 21h	/8051/tags/rel_12/rtl/verilog/