URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] - Rev 171

Rev	Log message	Author	Age	Path
134	fix bug in case execution of two data dependent instructions.	simont	7750d 00h	/8051/tags/rel_12/rtl/verilog/
133	fix bug in substraction.	simont	7750d 03h	/8051/tags/rel_12/rtl/verilog/
132	change branch instruction execution (reduse needed clock periods).	simont	7753d 18h	/8051/tags/rel_12/rtl/verilog/
128	chance idat_ir to 24 bit wide	simont	7763d 02h	/8051/tags/rel_12/rtl/verilog/
127	fix bug (cyc_o and stb_o)	simont	7763d 02h	/8051/tags/rel_12/rtl/verilog/
126	define OC8051_XILINX_RAMB added	simont	7763d 02h	/8051/tags/rel_12/rtl/verilog/
123	fiz bug iv pcs operation.	simont	7764d 21h	/8051/tags/rel_12/rtl/verilog/
122	deifne OC8051_ROM added	simont	7768d 01h	/8051/tags/rel_12/rtl/verilog/
121	Change pc add value from 23'h to 16'h	simont	7768d 01h	/8051/tags/rel_12/rtl/verilog/
120	defines for pherypherals added	simont	7768d 23h	/8051/tags/rel_12/rtl/verilog/